Under die surface mounted electrical elements
US9601423B1 · kind B1 · utility
4Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Dec 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4644
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A laminate includes a buildup layer having a top and a bottom and a solder mask contacting the top. The laminate also includes a circuit element disposed on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.