Semiconductor package with embedded components and method of making the same
US9601435B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2015 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Jan 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.