Array of non-volatile memory cells with ROM cells

US9601500B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Jinho Kim · Seoul, KR
• Vipin Tiwari · Dublin, US
• Nhan Do · Saratoga, US
• Xian Liu · Sunnyvale, US
• Xiaozhou Qian · Shanghai, CN
• Ning Bai · Shanghai, CN
• Kai Man Yue · Shanghai, CN

Key dates

• Filing date: Mar 4, 2015
• Grant date: Mar 21, 2017
• Expiry date: Mar 4, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6892
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.