Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer

US9606179B1 · kind B1 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Paul Alexander Cunningham · San Jose, US
• Steev Wilcox · San Jose, US
• Vivek Chickermane · Ithaca, US
• Krishna Vijaya Chakravadhanula · Vestal, US
• Brian Foutz · Charlottesville, US

Key dates

• Filing date: Jun 29, 2015
• Grant date: Mar 28, 2017
• Expiry date: Jun 29, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318558
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a serializer-deserializer in conjunction with a second XOR decompressor in a second stage.