Pseudo tester-per-site functionality on natively tester-per-pin automatic test equipment for semiconductor test
US9606183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2012 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Sep 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for testing devices are presented. Embodiments of the present invention use a central controller to coordinate the testing of a plurality of devices under test as well as a plurality of channel circuits that are each operable to be coupled to at least one I/O pin of a device under test of the aforementioned plurality of devices under test. Also, embodiments of the present invention include a plurality of intermediate processors that are each coupled to the central controller and operable to receive and send control signals. These intermediate processors are each coupled to a different set of channel circuits of the plurality of channel circuits and are operable to execute their own instantiation of a test program that is independent of any other intermediate processor of the plurality of intermediate processors for the testing of a device under test associated therewith.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.