Highly integrated scalable, flexible DSP megamodule architecture

US9606803B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Timothy David Anderson · University Park, US
• Joseph Zbiciak · San Jose, US
• Duc Quang Bui · Grand Prairie, US
• Abhijeet Ashok Chachad · Plano, US
• Kai Chirca · Dallas, US
• Naveen Bhoria · Plano, US
• Matthew D. Pierson · Sachse, US
• Daniel Wu · Dallas, US
• Ramakrishnan Venkatasubramanian · Plano, US

Key dates

• Filing date: Jul 15, 2014
• Grant date: Mar 28, 2017
• Expiry date: Dec 21, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03H2017/0298
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.