Insulator void aspect ratio tuning by selective deposition
US9607881B2 · kind B2 · utility
10Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2014 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Jul 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a structure conductive lines disposed in a base layer and separated by a first region. Pillars are each disposed over a respective one of the conductive lines. A dielectric fill layer is disposed over the pillars and extending between the pillars into the first region, and a void is disposed in the dielectric fill layer in the first region between the conductive lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.