Stress relieving through-silicon vias
US9607890B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2013 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Nov 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and systems for stress relieving through-silicon vias are disclosed and may include forming a semiconductor device comprising a stress relieving stepped through-silicon-via (TSV), said stress relieving stepped TSV being formed by: forming first mask layers on a top surface and a bottom surface of a silicon layer, forming a via hole through the silicon layer at exposed regions defined by the first mask layers, and removing the first mask layers. The formed via hole may be filled with metal, second mask layers may be formed covering top and bottom surfaces of the silicon layer and a portion of top and bottom surfaces of the metal filling the formed via hole, and metal may be removed from the top and bottom surfaces of the metal exposed by the second mask layers to a depth of less than half a thickness of the silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.