Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FINFET technology
US9607901B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2015 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | May 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.