Semiconductor structure with a doped region between two deep trench isolation structures
US9608105B2 · kind B2 · utility
6Cited by
4References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 4, 2015 |
| Grant date | Mar 28, 2017 |
| Priority date | — |
| Expiry date | Jun 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.