Network processor with distributed trace buffers
US9612934B2 · kind B2 · utility
2Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2011 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Jul 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network processor includes a cache and a several groups of processors for accessing the cache. A memory interconnect provides for connecting the processors to the cache via a plurality of memory buses. A number of trace buffers are also connected to the bus and operate to store information regarding commands and data transmitted across the bus. The trace buffers share a common address space, thereby enabling access to the trace buffers as a single entity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.