Memory systems and methods involving high speed local address circuitry
US9613670B2 · kind B2 · utility
24Cited by
10References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2016 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Mar 11, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of memory and memory operation are disclosed, such as providing a circuit including a local address driver voltage source for memory decoding. In one exemplary implementation, an illustrative circuit may comprise a first buffer and a capacitor. The first buffer may comprise a power input and a ground input. The capacitor may comprise a first terminal connected to the power input of the first buffer and a second terminal connected to the ground input of the first buffer. When the first buffer draws a current from the power input, at least a portion of the current may be supplied by the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.