Methods of forming MIS contact structures on transistor devices in CMOS applications
US9613855B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2016 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Apr 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method that includes, among other things, forming first and second contact openings in a layer of insulating material that respectively expose a portion of first and second source/drain (S/D) regions of first and second transistors that are of the opposite type, forming first, second and third layers of material within each of the first and second contact openings, and forming an implant masking layer that masks the first contact opening while leaving the second contact opening exposed for further processing. The method also includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, removing the implant masking layer and forming a conductive material in both the first and second contact openings so as to define first and second MIS contact structures positioned in the first and second contact openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.