De-integrated trench formation for advanced MRAM integration
US9614143B2 · kind B2 · utility
12Cited by
10References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 9, 2015 |
| Grant date | Apr 4, 2017 |
| Priority date | — |
| Expiry date | Jun 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
Abstract
A semiconductor device may include a magnetoresistive random-access memory (MRAM) trench having a first conductive barrier liner and a second conductive barrier liner. The MRAM trench may land on a hard mask of a magnetic tunnel junction (MTJ) within an MTJ region of the semiconductor device. The semiconductor device may also include a logic trench having the first conductive barrier liner. The semiconductor device may further include a logic via having the first conductive barrier liner. The logic via may land on a first portion of a conductive interconnect (Mx) within a logic region of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.