Two level memory full line writes
US9619396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2015 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | May 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.