Memory array architecture with two-terminal memory cells
US9620206B2 · kind B2 · utility
14Cited by
198References
19Claims
0Family size
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Key dates
| Filing date | Apr 21, 2015 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Apr 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.