Dual-sided integrated fan-out package
US9620465B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2016 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Jan 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein forming the RDL includes the steps of forming a seed layer, forming a first patterned mask over the seed layer, and performing a first metal plating. The method further includes forming through vias on top of a first portion of the RDL, wherein forming the through vias includes forming a second patterned mask over the seed layer and the RDL, and performing a second metal plating. The method further includes attaching a chip to a second portion of the RDL, and encapsulating the chip and the through vias in an encapsulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.