System and method for memory command queue management and configurable memory status checking
US9626106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jul 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/079
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such responsibility. Further, the memory integrated circuit chips may send an indication of an error in executing the commands, thereby relieving the controller from constant polling of the memory integrated circuit chips as to status.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.