Page management approach to fully utilize hardware caches for tiled rendering
US9626735B2 · kind B2 · utility
6Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2013 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jul 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/122
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.