Static random access memory layout structure
US9627036B2 · kind B2 · utility
2Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Aug 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.