Memory device and stress testing method of same
US9627091B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jul 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in rows and columns, a plurality of word lines extending in a row direction and coupled to respective rows of the memory cells, and a plurality of local bit lines extending in a column direction and coupled to respective columns of the memory cells. The control unit is configured to program a selected one of the rows of memory cells to have a predetermined pattern of digital states, couple selected ones of the local bit lines to a global bit line and couple unselected ones of the local bit lines to ground based on the predetermined pattern, apply a stress voltage to the global bit line, and after a predetermined period of time, sense the digital states of the selected row of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.