Method for manufacturing a chip package having a coating layer
US9627228B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a chip package structure having a coating layer is provided. At least one chip package structure is mounted onto a terminal-protection film. The chip package structure has a top side, a back side opposite to the top side and a plurality of lateral sides. A plurality of terminals is disposed on the back side. The terminal-protection film at least partially seals the back side. A coating layer is formed over the top side, the lateral sides and a periphery region of the chip package structure, wherein the coating layer is not formed on the back side and the terminals. The terminal-protection film is debonded from the chip package structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.