Forming array contacts in semiconductor memories
US9627251B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Sep 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.