D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies
US9627408B1 · kind B1 · utility
3Cited by
5References
27Claims
0Family size
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Key dates
| Filing date | Sep 8, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Sep 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/987
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A library of a DFM-improved standard logic cells (including D flip-flop cells) that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.