Non-planar transistor and method of forming the same
US9627541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jun 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.