Accelerated physical secure erase
US9633738B1 · kind B1 · utility
13Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2016 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Jun 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage system includes a controller that is configured to make host data inaccessible. To do so, the controller may control power control circuitry to supply pulses to storage locations storing host data. The pulses may include flash write pulses but no erase pulses, or a combination of flash write pulses and erase pulses. If erase pulses are supplied, the number of the erase pulses may be less than the number supplied for performance of a default erase operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.