Semiconductor structure including a nonvolatile memory cell and method for the formation thereof

US9634017B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Peter Baars · Dresden, DE
• Hans-Juergen Thees · Dresden, DE

Key dates

• Filing date: Dec 4, 2015
• Grant date: Apr 25, 2017
• Expiry date: Dec 4, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/665
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor structure includes a nonvolatile memory cell including a first nonvolatile bit storage element and a second nonvolatile bit storage element which have a common source region provided in a semiconductor material and a common control gate structure. Each nonvolatile bit storage element includes a drain region, a channel region, a select gate structure, a floating gate structure and an erase gate structure. The channel region has a select gate side portion and a floating gate side portion. The select gate structure is provided at the select gate side portion of the channel region and the floating gate structure is provided at the floating gate side portion of the channel region. The erase gate structure is provided above the select gate structure and adjacent the floating gate structure. The control gate structure extends above the floating gate structures of the first and second nonvolatile bit storage elements.