Integrated controller for training memory physical layer interface
US9639495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2014 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Aug 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.