Nonvolatile static random access memory (NVSRAM) system having a static random access memory (SRAM) array and a resistive memory array
US9640256B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | May 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) device includes a static random access memory (SRAM) array, and a resistive memory (resistive memory) array. A first set of programmable resistive elements in the resistive memory array are used to store data from memory cells in the SRAM array. Sense amplifier circuitry is couplable to the SRAM array and the resistive memory array. An arbiter is configured to assert an resistive memory enable signal to couple the sense amplifier circuitry to the resistive memory array and decouple the sense amplifier circuitry from the SRAM array during a resistive memory read operation, and to couple the sense amplifier to the SRAM array and decouple the sense amplifier circuitry from the resistive memory array during an SRAM read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.