Single-poly nonvolatile memory cell
US9640259B2 · kind B2 · utility
53Cited by
6References
8Claims
0Family size
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Key dates
| Filing date | Nov 20, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Nov 20, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.