Semiconductor device with buried gates and bit line contacting peripheral gate
US9640626B2 · kind B2 · utility
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Key dates
| Filing date | Feb 3, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Feb 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
Abstract
A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.