Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device

US9640636B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Steven Bentley · Menands, US
• John H. Zhang · Fishkill, US
• Kwan-Yong Lim · Plano, US
• Hiroaki Niimi · Cohoes, US

Key dates

• Filing date: Jun 2, 2016
• Grant date: May 2, 2017
• Expiry date: Jun 2, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/252

Abstract

One illustrative method disclosed herein includes, among other things, forming an initial vertically oriented channel semiconductor structure having a first height above a substrate, forming a sacrificial spacer structure adjacent the initial vertically oriented channel semiconductor structure and, with the sacrificial spacer in position, performing at least one process operation to define a self-aligned bottom source/drain region for the device that is self-aligned with respect to the sacrificial spacer structure, forming an isolation region in the trench and forming a bottom source/drain electrode above the isolation region. The method also includes removing the sacrificial spacer structure and forming a bottom spacer material around the vertically oriented channel semiconductor structure above the bottom source/drain electrode.