Bandwidth limiting methods for GaN power transistors
US9641163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2014 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | May 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/21142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor package includes a transistor and one or more bandwidth limiting matching networks. The one or more bandwidth limiting matching networks are coupled to one of a control contact and an output contact of the transistor in order to limit the gain response of the transistor outside of a predetermined frequency band. Specifically, the transistor package has a gain roll-off greater than 0.5 dB within 200 MHz of the predetermined frequency band, while providing signal losses less than 1.0 dB inside the predetermined frequency band at a power level greater than 240 W. By providing the bandwidth limiting matching networks in the transistor package, the gain response of the transistor may be appropriately limited in order to comply with the spectral masking requirements of one or more wireless communications standards, for example, Long Term Evolution (LTE) standards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.