Post-routing structural netlist optimization for circuit designs
US9646126B1 · kind B1 · utility
5Cited by
2References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 27, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Mar 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Post-routing processing of a circuit design may include determining, using a processor, a baseline delay for a path of a routed circuit design, comparing, using the processor, the baseline delay of the path with a timing constraint of the path, and selectively applying, according to the comparing, a structural netlist optimization to the path resulting in an optimized path using a processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.