Memory cell with improved write margin
US9646681B1 · kind B1 · utility
15Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2016 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Apr 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory and a method for operating a memory are provided. The memory includes a memory cell having a first circuit to store a bit and a second circuit to decouple the stored bit from a power supply and from a return. The method includes storing a bit in a memory cell by a first circuit and decoupling the stored bit from a power supply and a return by a second circuit. Another memory is provided. The memory includes a memory cell having means for storing a bit by a feedback and means for disabling the feedback.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.