Multi-bank memory device and system
US9653148B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Feb 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a common data bus, a plurality of memory banks and a control circuit. The memory banks are coupled to the common data bus. The memory banks share the common data bus. Each of the memory banks includes a storage device and a data register. The data register is coupled between the storage device the common data bus, and is arranged for storing data read from the storage device. The control circuit is coupled to storage devices and data registers of the memory banks, and is arranged for referring to an address signal and an access signal to control the storage device of said each memory bank to output the data to the corresponding data register, and referring to the address signal and a programmable latency time to control the data registers to output data from the memory banks to the common data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.