Memory array having segmented row addressed page registers
US9653151B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Oct 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B99/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The access speeds of new memory technologies may not be compatible with product specifications of existing memory technologies such as DRAM, SRAM, and FLASH technologies. Their electrical parameters and behaviors are different such that they cannot meet existing memory core specifications without new architectures and designs to overcome their limitations. New memories such as STT-MRAM, Resistive-RAM, Phase-Change RAM, and a new class of memory called Vertical Layer Thyristor (VLT) RAM requires new read sensing and write circuits incorporating new voltage or current levels and timing controls to make these memory technologies work in today's systems. Systems and methods are provided for rendering the memory cores of these technologies transparent to existing peripheral logic so that they can be easily integrated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.