Determination of word line to word line shorts between adjacent blocks
US9653175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Oct 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.