Fabrication of nano-sheet transistors with different threshold voltages
US9653289B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Sep 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/43
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.