Individually read-accessible twin memory cells
US9653470B2 · kind B2 · utility
1Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2015 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Mar 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.