Methods of fabricating isolation regions of semiconductor devices and structures thereof
US9653543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Feb 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.