Vertical transistor with a body contact for back-biasing
US9653575B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | May 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer, the sacrificial layer disposed on hardmask arranged on a substrate, and the substrate including a bulk semiconductor layer, a buried oxide layer arranged on the bulk semiconductor layer, and a semiconductor layer arranged on the buried oxide layer; forming oxide spacers on sidewalls of the opening in the sacrificial layer; using the oxide spacers as a pattern to etch a trench through the substrate, the trench stopping at a region within the bulk semiconductor layer; and depositing a conductive material in the trench to form the substrate contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.