Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices

US9653583B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Wei Zhao · Zhuhai, CN
• Haiting Wang · Clifton Park, US
• Hongliang Shen · Ballston Lake, US
• Zhenyu Hu · Leonberg, DE
• Min-hwa Chi · Palo Alto, US

Key dates

• Filing date: Aug 2, 2016
• Grant date: May 16, 2017
• Expiry date: Aug 2, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

One illustrative method disclosed herein includes, among other things, forming a first gate structure above a fin, forming epi semiconductor material on the fin, performing at least one first etching process through a patterned sacrificial layer of material to remove at least a gate cap layer and sacrificial gate materials of the first gate structure so as to define a first isolation cavity that exposes the fin while leaving the second gate structure intact, performing at least one second etching process through the first isolation cavity to remove at least a portion of a vertical height of the fin and thereby form a first isolation trench, removing the patterned sacrificial layer of material, and forming a layer of insulating material above the epi semiconductor material and in the first isolation trench and in the first isolation cavity.