Method for fabricating a shallow and narrow trench FET and related structures
US9653597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2010 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | May 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.