Consecutive bit error detection and correction
US9654143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Oct 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/29
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.