Progressive effort decoder architecture
US9654144B2 · kind B2 · utility
2Cited by
4References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Jan 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3715
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.