Thermally-aware throttling in a three-dimensional processor stack
US9658663B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 22, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Sep 22, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3-D) processor stack includes a plurality of processor cores implemented in a plurality of layers. A controller is to selectively throttle one or more of a plurality of processor cores in response to detecting a thermal event. The controller selectively throttles the one or more of the plurality of processor cores based on values of thermal couplings between the plurality of layers and based on measures of criticality of threads executing on the plurality of processor cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.