Semiconductor packages, methods of manufacturing the same, electronic systems including the same, and memory cards including the same
US9659833B2 · kind B2 · utility
1Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Aug 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes an adhesive member disposed on a package substrate to have a trapezoid cross-section view, and a semiconductor chip disposed on the adhesive member and attached to the package substrate by the adhesive member. The semiconductor chip has a first surface and a second surface facing the first surface, and the second surface of the semiconductor chip contacts the adhesive member. The semiconductor chip includes a tension supplement pattern attached to the second surface and spaced apart from the package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.