Wafer-scale marking systems and related methods
US9659876B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Jul 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54486
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of wafer-scale marking includes coupling a first marking mask over a semiconductor wafer having unsingulated semiconductor devices thereon. The first marking mask has a plurality of first stencils therethrough and a surface of the wafer is plasma etched through the first stencils to form first markings in the surface. A second marking mask is coupled over the surface and includes a plurality of second stencils therethrough. The surface is plasma etched through the second stencils to form second markings in the surface. In implementations the first marking mask and second marking mask are simultaneously coupled over the surface and the first markings and second markings are simultaneously formed. In implementations a plurality of first windows of the first marking mask are aligned with the plurality of second stencils while a plurality of second windows of the second marking mask are aligned with the plurality of first stencils.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.