Semiconductor devices including stair step structures, and related methods
US9659950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Oct 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.